The present invention concerns a sense amplifier of a semiconductor memory, and particularly a circuit for optimizing the operation of the sense amplifier by controlling the output thereof.
Generally, a semiconductor memory includes a part for storing data (i.e., memory cell groups), a selecting part for selectively storing and/or reading out data into and/or from an addressed memory location (i.e., decoder), a part for sensing the signal state of the input/output data (i.e., sense amplifier), and a part for passing the data (i.e., data bus). Presently, some of the important problems to solve concerning such a semiconductor memory are to make it have a large scale data storing capacity, improve operating speed thereof, and reduce the undesired power consumption.
Furthermore, the part for sensing the signal state of the input/output data, i.e., a sense amplifier, amplifies the data retrieved from a selected memory cell by means of voltage difference and then delivered to a data output buffer. Hence, the operating efficiency of the memory depends on whether the sense amplifier properly works within the optimum time or not.
Referring to FIG. 1 for schematically showing the construction of a conventional semiconductor memory, the address signals converted through the address buffer 200 into a CMOS level (i.e., logic high state is 5V and logic low state is 0V) are delivered to the row and column decoders 300 and 400, which select a memory cell of the memory cell array 100. The data retrieved from a selected memory cell is output through the sense amplifier 600, data latch circuit 700 and data output buffer 800 to the I/O pad 900. An address transition detector (ATD) for receiving the signal of the address buffer 200 detects the transition of the address signal so as to control the input/output of the sense amplifier 600 and the data latch circuit 700. The output signal of the ATD 500, i.e., address transition detection signal, is used to control the data lines between the sense amplifier 600 and the data latch circuit 700, as shown in FIG. 2.
Referring to FIG. 2, there are provided a pair of transfer PMOS transistors 63 and 64 in a pair of data lines 61 and 62, disposed between the sense amplifier 600 and the data latch circuit 700. The gates of the transfer transistors are connected with the output signal, of the ATD 500.
In such a conventional system for controlling the output of the sense amplifier 600 by using the ATD 500, there may occur the following two problems.
First, in the event that the sense amplifier 600 is continuously enabled even after generation of the data, if data passes through the I/O pad 900, the voltage swing from logic "low" state to logic "high" state or vice versa in the I/O pad 900 causes noise which may affect the sense amplifier 600.
Second, in the event that the sense amplifier 600 is disabled by the ATD signal after the generation of data, since the sense amplifier 600 is in the active state during the lag between the data outputting and the disabling thereof, the reduction of power consumption during this lag is limited.
Consequently, the time point at which the sense amplifier produces output data must be separated from the time point at which the data is finally retrieved at the I/O pad, in order to prevent the noise which may be induced by the I/O pad 900 to the sense amplifier and reduce the power consumption during the operation of the sense amplifier 600.